Computer aided design (CAD) systems are used to design complex integrated circuits or dies. Schematic designs are created using such CAD systems which describe the integrated circuit components and interconnections between components which will be fabricated within integrated circuit dies.
CAD systems typically store the circuit designs in memory within a hierarchical form or a flat form. The hierarchical structure of a circuit design description is represented by parent-child relationships. The hierarchical representational system breaks the system being designed into a top level module or modules which include smaller blocks within them that make up the top level module. The overall system is the top most module. The top level module does not usually include any reference to gates or other circuits, but rather refers more to the function accomplished by the top or macro level component(s) which are the largest functional component(s) in the design.
Each next lower level of module includes a smaller number of modules until the level or subset of the total system is reached which contains only primitives or the most basic circuit sub-components, such as a NMOS transistor or a resistor. A hierarchical representation of a circuit design allows designers to solve complex circuit design problems using the divide and conquer approach. Complexity is reduced to the point where the overall design can be understood without being obscured by the details of a very large circuit design. High levels of abstraction permits a designer to understand the system under development at many levels.
Hierarchical designs can be organized in a number of ways such as “top down” and “bottom up”. The top down methodology starts by defining the top level blocks and identifying the sub-blocks necessary to built the top level blocks and further subdivides these sub-blocks into leaf cells, which are the lowest level of a circuit design. For example, a leaf cell may be a cell within a hierarchical representation that does not contain any other cells, thus it is the lowest level in the hierarchical representation. The subdivision of lower components into lower cells or modules usually stops when there is no further significant advantage in reusability and comprehensibility of detail.
The bottom-up design methodology approach begins from the leaf cells, which are the terminal end of a branch of cells in a tree type circuit hierarchy and thus represent the “bottom” of the tree schematic. Designers begin to construct the higher cell blocks in the circuit design hierarchy using available leaf cells. A designer continues building the next higher blocks until the final design is realized.
In practice neither bottom-up or top-down approach is used alone. A combination of both approaches is typically used. Usually when decomposing a hierarchy, the design is partitioned into several sub-modules based on their functionality. This is sometimes known as vertical partitioning.
The second type of CAD system design relationship uses a flat representation of circuit components in a design. Each component connects directly to another component, rather than being defined in a modular approach seen in the hierarchical system, where modules connect to other modules.
Once a schematic circuit design has been created using CAD systems, it is output as a netlist. Netlists are computer files which contain a textual or character based description of the integrated circuits and the relationships between the circuits or cells that comprise a device described by the netlist or schematic design.
Netlists can be organized in the hierarchical or the flat form. A flat data netlist contains multiple copies of the circuit modules without boundary descriptions found in hierarchical representations, usually consisting of module or cell instance names. For example, a flat data netlist will list one or more flat paths describing a string of components that are connected at a highest level in the circuit design hierarchy through a lowest component. In other words, a flat path it is a path statement from a starting place, usually the highest point in that particular path, to a specified endpoint marker or either the lowest or bottom-most primitive component in a particular current or circuit path. The start or stop points can also be selected based upon a desire to test a segment within a larger circuit path.
CAD tools are commonly linked together and must be able to convert from one format to another format depending on the stage of the integrated circuit design process. Hierarchical netlists are typically used when designing the integrated circuit as that format helps designers easily understand how the different components in the system being designed work together. Flat data netlists are usually required when other CAD tools are used such as timing verification, circuit simulation and circuit placement and routing tools.
One type of electronic design automation (EDA) system used to evaluate and perform error checking on the netlist after the design is compiled includes electrical rule check (ERC) programs. ERC programs look at a netlist schematic and make sure markers or other specific components are present within the schematic design and then evaluates how the system design works with respect to the markers placed in the netlist. The ERC system focuses on looking for a particular electrical marker/component such as high voltage (HV) net markers, super voltage (SV) net markers, pad markers, super voltage fuse markers, negative voltage net markers for lower voltage charge pumps (lower than zero volts) and any other type of marker.
ERC systems require a flat data netlist representation to perform rule checking in some cases. (Some checks are done solely on a hierarchical representation, such as verification that a particular marker is at all levels of the hierarchy) ERC systems which must scan through each instance of a cell or combination of cells in a large integrated circuit design would require very large amounts of processing time to perform ERC functional checks on hierarchical lists. Consequently, a hierarchical netlist representation must be converted to a flat data netlist to decrease ERC processing time. An ERC system starts with a beginning reference point and then performs rule checks for circuit components that are listed from the reference point along the absolute path statement. A reference point may be a cell description, net descriptor (an electrical connection, e.g. “wire” between components or cells), HV marker or any specified circuit component or group of circuit components and/or markers and/or net descriptors. The ERC system evaluates how a marker or circuit component interacts with the rest of the design by looking for failure modes that occur when certain combinations are present, such as improper associations of a component with a marker e.g. pad marker associated with a circuit component which is incompatible with the pad. Markers (also called flat data search targets with respect to flat data search programs) are used by ERC programs to identify circuit components within a hierarchical netlist which are being evaluated for improper combinations with other circuit components during ERC checks.
The flat data netlist used in ERC systems includes an absolute path down to the marker via instance names. Flat net information includes a path statement for every marker along with net names without listing cell instance identifiers in the path description usually from a top level to a lower level cell or component in a circuit schematic which lie on a net. Cell instances are required to describe a hierarchy of larger to smaller cells.
Conventional flat data programs perform searches in a hierarchical netlist to assemble flat path statements. Such a program typically starts at a top level cell then looks at every instance in that cell progressing or traversing down through each subsequent level in the hierarchical circuit schematic or netlist until the flat data search system has assembled a flat description for the netlist which includes all the markers throughout the entire system. Such flat data programs assembles path statements as the program progresses from a top descriptor to a bottom descriptor. This can take a great deal of time when dealing with very large systems such as a DRAM. For example, a DRAM can have hundreds of millions of cells which the flat list search system must go through and create an absolute path statement to populate the flat data file. It is not uncommon for a conventional flatlist system to take three for four days to go through a DRAM circuit to assemble the flat data with flat path statement for each net running from one specified point to another specified point. Thus, a need exists to improve the ability for flat data programs to assemble flat data required for rapid development of integrated circuits.